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NXP Semiconductors /MKL26Z4 /NVIC /NVIC_ICER

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Interpret as NVIC_ICER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CLRENA0 0 (0)CLRENA1 0 (0)CLRENA2 0 (0)CLRENA3 0 (0)CLRENA4 0 (0)CLRENA5 0 (0)CLRENA6 0 (0)CLRENA7 0 (0)CLRENA8 0 (0)CLRENA9 0 (0)CLRENA10 0 (0)CLRENA11 0 (0)CLRENA12 0 (0)CLRENA13 0 (0)CLRENA14 0 (0)CLRENA15 0 (0)CLRENA16 0 (0)CLRENA17 0 (0)CLRENA18 0 (0)CLRENA19 0 (0)CLRENA20 0 (0)CLRENA21 0 (0)CLRENA22 0 (0)CLRENA23 0 (0)CLRENA24 0 (0)CLRENA25 0 (0)CLRENA26 0 (0)CLRENA27 0 (0)CLRENA28 0 (0)CLRENA29 0 (0)CLRENA30 0 (0)CLRENA31

CLRENA11=0, CLRENA24=0, CLRENA4=0, CLRENA29=0, CLRENA19=0, CLRENA17=0, CLRENA18=0, CLRENA8=0, CLRENA16=0, CLRENA25=0, CLRENA30=0, CLRENA27=0, CLRENA10=0, CLRENA20=0, CLRENA0=0, CLRENA23=0, CLRENA31=0, CLRENA26=0, CLRENA14=0, CLRENA3=0, CLRENA1=0, CLRENA7=0, CLRENA15=0, CLRENA28=0, CLRENA9=0, CLRENA21=0, CLRENA2=0, CLRENA12=0, CLRENA13=0, CLRENA6=0, CLRENA5=0, CLRENA22=0

Description

Interrupt Clear Enable Register

Fields

CLRENA0

DMA channel 0 transfer complete and error interrupt clear-enable bit

0 (0): write: no effect; read: DMA channel 0 transfer complete and error interrupt disabled

1 (1): write: disable DMA channel 0 transfer complete and error interrupt; read: DMA channel 0 transfer complete and error interrupt enabled
CLRENA1

DMA channel 1 transfer complete and error interrupt clear-enable bit

0 (0): write: no effect; read: DMA channel 1 transfer complete and error interrupt disabled

1 (1): write: disable DMA channel 1 transfer complete and error interrupt; read: DMA channel 1 transfer complete and error interrupt enabled
CLRENA2

DMA channel 2 transfer complete and error interrupt clear-enable bit

0 (0): write: no effect; read: DMA channel 2 transfer complete and error interrupt disabled

1 (1): write: disable DMA channel 2 transfer complete and error interrupt; read: DMA channel 2 transfer complete and error interrupt enabled
CLRENA3

DMA channel 3 transfer complete and error interrupt clear-enable bit

0 (0): write: no effect; read: DMA channel 3 transfer complete and error interrupt disabled

1 (1): write: disable DMA channel 3 transfer complete and error interrupt; read: DMA channel 3 transfer complete and error interrupt enabled
CLRENA4

Reserved iv 20 interrupt clear-enable bit

0 (0): write: no effect; read: Reserved iv 20 interrupt disabled

1 (1): write: disable Reserved iv 20 interrupt; read: Reserved iv 20 interrupt enabled
CLRENA5

FTFA command complete and read collision interrupt clear-enable bit

0 (0): write: no effect; read: FTFA command complete and read collision interrupt disabled

1 (1): write: disable FTFA command complete and read collision interrupt; read: FTFA command complete and read collision interrupt enabled
CLRENA6

low-voltage detect and low-voltage warning interrupt clear-enable bit

0 (0): write: no effect; read: low-voltage detect and low-voltage warning interrupt disabled

1 (1): write: disable low-voltage detect and low-voltage warning interrupt; read: low-voltage detect and low-voltage warning interrupt enabled
CLRENA7

low leakage wakeup interrupt clear-enable bit

0 (0): write: no effect; read: low leakage wakeup interrupt disabled

1 (1): write: disable low leakage wakeup interrupt; read: low leakage wakeup interrupt enabled
CLRENA8

inter-integrated circuit 0 interrupt clear-enable bit

0 (0): write: no effect; read: inter-integrated circuit 0 interrupt disabled

1 (1): write: disable inter-integrated circuit 0 interrupt; read: inter-integrated circuit 0 interrupt enabled
CLRENA9

inter-integrated circuit 1 interrupt clear-enable bit

0 (0): write: no effect; read: inter-integrated circuit 1 interrupt disabled

1 (1): write: disable inter-integrated circuit 1 interrupt; read: inter-integrated circuit 1 interrupt enabled
CLRENA10

serial peripheral interface 0 interrupt clear-enable bit

0 (0): write: no effect; read: serial peripheral interface 0 interrupt disabled

1 (1): write: disable serial peripheral interface 0 interrupt; read: serial peripheral interface 0 interrupt enabled
CLRENA11

serial peripheral interface 1 interrupt clear-enable bit

0 (0): write: no effect; read: serial peripheral interface 1 interrupt disabled

1 (1): write: disable serial peripheral interface 1 interrupt; read: serial peripheral interface 1 interrupt enabled
CLRENA12

UART0 status and error interrupt clear-enable bit

0 (0): write: no effect; read: UART0 status and error interrupt disabled

1 (1): write: disable UART0 status and error interrupt; read: UART0 status and error interrupt enabled
CLRENA13

UART1 status and error interrupt clear-enable bit

0 (0): write: no effect; read: UART1 status and error interrupt disabled

1 (1): write: disable UART1 status and error interrupt; read: UART1 status and error interrupt enabled
CLRENA14

UART2 status and error interrupt clear-enable bit

0 (0): write: no effect; read: UART2 status and error interrupt disabled

1 (1): write: disable UART2 status and error interrupt; read: UART2 status and error interrupt enabled
CLRENA15

Analog-to-digital converter 0 interrupt clear-enable bit

0 (0): write: no effect; read: Analog-to-digital converter 0 interrupt disabled

1 (1): write: disable Analog-to-digital converter 0 interrupt; read: Analog-to-digital converter 0 interrupt enabled
CLRENA16

Comparator 0 interrupt clear-enable bit

0 (0): write: no effect; read: Comparator 0 interrupt disabled

1 (1): write: disable Comparator 0 interrupt; read: Comparator 0 interrupt enabled
CLRENA17

Timer PWM module 0 interrupt clear-enable bit

0 (0): write: no effect; read: Timer PWM module 0 interrupt disabled

1 (1): write: disable Timer PWM module 0 interrupt; read: Timer PWM module 0 interrupt enabled
CLRENA18

Timer PWM module 1 interrupt clear-enable bit

0 (0): write: no effect; read: Timer PWM module 1 interrupt disabled

1 (1): write: disable Timer PWM module 1 interrupt; read: Timer PWM module 1 interrupt enabled
CLRENA19

Timer PWM module 2 interrupt clear-enable bit

0 (0): write: no effect; read: Timer PWM module 2 interrupt disabled

1 (1): write: disable Timer PWM module 2 interrupt; read: Timer PWM module 2 interrupt enabled
CLRENA20

real time clock alarm interrupt clear-enable bit

0 (0): write: no effect; read: real time clock alarm interrupt disabled

1 (1): write: disable real time clock alarm interrupt; read: real time clock alarm interrupt enabled
CLRENA21

real time clock seconds interrupt clear-enable bit

0 (0): write: no effect; read: real time clock seconds interrupt disabled

1 (1): write: disable real time clock seconds interrupt; read: real time clock seconds interrupt enabled
CLRENA22

periodic interrupt timer all channels interrupt clear-enable bit

0 (0): write: no effect; read: periodic interrupt timer all channels interrupt disabled

1 (1): write: disable periodic interrupt timer all channels interrupt; read: periodic interrupt timer all channels interrupt enabled
CLRENA23

integrated interchip sound 0 interrupt clear-enable bit

0 (0): write: no effect; read: integrated interchip sound 0 interrupt disabled

1 (1): write: disable integrated interchip sound 0 interrupt; read: integrated interchip sound 0 interrupt enabled
CLRENA24

universal serial bus on the go interrupt clear-enable bit

0 (0): write: no effect; read: universal serial bus on the go interrupt disabled

1 (1): write: disable universal serial bus on the go interrupt; read: universal serial bus on the go interrupt enabled
CLRENA25

digital-to-analog converter 0 interrupt clear-enable bit

0 (0): write: no effect; read: digital-to-analog converter 0 interrupt disabled

1 (1): write: disable digital-to-analog converter 0 interrupt; read: digital-to-analog converter 0 interrupt enabled
CLRENA26

touch sensing input interrupt clear-enable bit

0 (0): write: no effect; read: touch sensing input interrupt disabled

1 (1): write: disable touch sensing input interrupt; read: touch sensing input interrupt enabled
CLRENA27

multipurpose clock generator interrupt clear-enable bit

0 (0): write: no effect; read: multipurpose clock generator interrupt disabled

1 (1): write: disable multipurpose clock generator interrupt; read: multipurpose clock generator interrupt enabled
CLRENA28

Low-Power Timer interrupt clear-enable bit

0 (0): write: no effect; read: Low-Power Timer interrupt disabled

1 (1): write: disable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled
CLRENA29

Reserved iv 45 interrupt clear-enable bit

0 (0): write: no effect; read: Reserved iv 45 interrupt disabled

1 (1): write: disable Reserved iv 45 interrupt; read: Reserved iv 45 interrupt enabled
CLRENA30

PORTA pin detect interrupt clear-enable bit

0 (0): write: no effect; read: PORTA pin detect interrupt disabled

1 (1): write: disable PORTA pin detect interrupt; read: PORTA pin detect interrupt enabled
CLRENA31

PORTC and PORTD pin detect interrupt clear-enable bit

0 (0): write: no effect; read: PORTC and PORTD pin detect interrupt disabled

1 (1): write: disable PORTC and PORTD pin detect interrupt; read: PORTC and PORTD pin detect interrupt enabled

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data